A 21.4 Pw/Frame-Pixel Pwm Image Sensor With Sub-Threshold Leakage Reduction And Two-Step Readout

In this work we present a sub-1V pulse-width-modulation (PWM) CMOS image sensor. Ultra-low power consumption is achieved through the sub-threshold pixel bias, time-to-digital conversion and the array-level asynchronous counter. The 2-step readout scheme is adopted to improve the frame rate up to 68 fps. The prototype chip with 64 x 64 array has been fabricated in a 0.18 mu m 1P6M CMOS process. Minimum functional analog supply of 0.36V can be achieved, and the whole chip consumes only 1.14 mu W at 13 fps, or 21.4 pW/frame-pixel. The dynamic range and FPN are measured to be 70 dB and 0.49% respectively.