A 520k (18900, 17010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory.

Kin-Chu Ho,Chih-Lung Chen,Hsie-Chia Chang

IEEE Transactions on Very Large Scale Integration (VLSI) Systems（2016）

引用 41|浏览82

暂无评分

摘要

Although Latin square is a well-known algorithm to construct low-density parity-check (LDPC) codes for satisfying long code length, high code-rate, good correcting capability, and low error floor, it has a drawback of large submatrix that the hardware implementation will be suffered from large barrel shifter and worse routing congestion in fitting NAND flash applications. In this paper, a top-down...

查看译文

关键词

Parity check codes,Decoding,Arrays,Ash,Dispersion,Bit error rate,Hardware

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要