An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection

An all-digital phase-locked loop (ADPLL) with a bang-bang phase-frequency detector (BBPFD) that tracks the optimum loop gain for minimum jitter is proposed. The autocorrelation of the output of BBPFD indicates whether the bang-bang PLL (BBPLL) operates in the nonlinear regime or the random noise regime. An adaptive loop gain controller (ALGC) continuously evaluates the autocorrelation of the BBPFD output and adjusts the loop gain to make the autocorrelation zero. The digital loop filter (DLF) operates at higher than the reference clock frequency to reduce the loop latency and to mitigate the resolution of the digitally-controlled oscillator (DCO). The prototype chip has been fabricated in a 65-nm CMOS process. The core consumes 5 mW at 2.5 GHz and exhibits rms jitter of 1.72 ps.