Impact of die thinning on the thermal performance of a central TSV bus in a 3D stacked circuit

In three-dimensional integrated circuits (3DICs), aggressive wafer-thinning can lead to large thermal gradients. It is crucial to understand the interaction between process parameters, such as wafer thickness, and the temperature profile in order to design high-performance 3DICs. In this paper we examine how the temperature profile of through-silicon via (TSV) bus driver/receiver cells are impacted by die thinning. While die thinning limits the ability for heat to diffuse into the wafer, it can also decrease the capacitance of the TSV which in turn decreases the driver's power, leading to an overall lower working temperature in some circumstances. In this work we have investigated the thermal effects of stacking 2-8 thinned ICs with TSVs, over a range of die thicknesses from 100 µ m to 25 µ m . Decreasing the die thickness from 100 µ m to 50 µ m provided the best balance with a 20% reduction in bus power at a cost of less than a 2% increase in driver temperature for all cases between 2 and 8 tiers. HighlightsDie thinning generally leads to higher system temperatures.TSV bus capacitances decrease when dies are thinned.Decreased TSV bus capacitances lead to lower power dissipation.Die thinning can be used to simultaneously decrease both power and temperature.