A Delay Locked Loop with A Feedback Edge Combiner of Duty-Cycle Corrector with A 20%-80% Input Duty Cycle for Sdrams
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS（2016）
关键词
Delay locked loop (DLL),DDR type 4 (DDR4),double date rate (DDR) type 3 (DDR3),duty-cycle corrector (DCC),feedback edge combiner,fine phase mixer (FPM),synchronous dynamic random access memory (SDRAM),wide range
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