Effects of thickness and geometric variations in the oxide gate stack on the nonvolatile memory behaviors of charge-trap memory thin-film transistors

•Nonvolatile memory thin-film transistor using ZnO charge-trap layer was proposed.•Tunneling and charge-trap layer thicknesses were optimized for memory operations.•Geometry effect for the charge-trap layer was examined for circuit applications.•High-speed programing and long retention time were successfully obtained.•Drain-bias disturbance was effectively suppressed by optimum device designs.