ZNS/ZNMGSETE/ZNS II-VI Energy Barrier for INGAAS Substrates

InGaAs high mobility transistors presently provide the fastest speeds. As InGaAs nonvolatile memory field effect transistors (NVMFETs) are scaled down past 22 nm gate width, threshold voltage variation becomes a limiting factor. Replacing the amorphous SiO 2 or HfO 2 with a heteroepitaxial barrier stack the threshold voltage can be stabilized by minimizing the interface charge at the barrier-channel interface. The floating gate is comprised of individually germanium-oxide cladded germanium quantum dots. The tunneling layer is comprised of a quantum well stack of ZnSe / ZnS / ZnMgSeTe / ZnS / ZnSe . The magnesium incorporation increases the the energy barrier but introduces dislocation that can leak charge. The ZnS and ZnSe layers have a lower bandgap but a lower dislocation density to assist with gate leakage prevention. We present simulation and experimental C-V data on InGaAs FET and II-VI tunneling layer on an InGaAs substrate respectively.