A sub 100ns static 64k CMOS EPROM with on-chip test functions
Solid-State Circuits Conference. Digest of Technical Papers. 1983 IEEE International（1983）
Abstract
This report will cover the design of a sub 100ns 64K N-well CMOS EPROM with 1μW quiescent power dissipation. On-chip test circuits have been used to reduce the time required for testing and reliability screening. Typical access time is 80ns.
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Key words
chip,power dissipation
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