Demonstrating Production Quality Multiple Exposure Patterning Aware Routing For The 10nm Node

This paper reviews the escalation in design constraints imposed on 2nd level wiring by multiple patterning exposure techniques in the 10NM technology node (i.e. similar to 45nm wiring pitch) relative to the 14NM technology node (i.e. 64nm wiring pitch). Specifically, new challenges facing place-and-route tooling are outlined, solutions to overcome these challenges are reviewed, and a manufacturing ready implementation is demonstrated.