A full-chip DSA correction framework

The graphoepitaxy DSA process relies on lithographically created confinement wells to perform directed self-assembly in the thin film of the block copolymer. These self-assembled patterns are then etch transferred into the substrate. The conventional DUV immersion or EUV lithography is still required to print these confinement wells, and the lithographic patterning residual errors propagate to the final patterns created by DSA process. DSA proximity correction ( PC), in addition to OPC, is essential to obtain accurate confinement well shapes that resolve the final DSA patterns precisely. In this study, we proposed a novel correction flow that integrates our co-optimization algorithms, rigorous 2-D DSA simulation engine, and OPC tool. This flow enables us to optimize our process and integration as well as provides a guidance to design optimization. We also showed that novel RET techniques such as DSA-Aware assist feature generation can be used to improve the process window. The feasibility of our DSA correction framework on large layout with promising correction accuracy has been demonstrated. A robust and efficient correction algorithm is also determined by rigorous verification studies. We also explored how the knowledge of DSA natural pitches and lithography printing constraints provide a good guidance to establish DSA-Friendly designs. Finally application of our DSA full-chip computational correction framework to several real designs of contact-like holes is discussed. We also summarize the challenges associated with computational DSA technology.