E-Beam Invasiveness On 65 Nm Complementary Metal-Oxide Semiconductor Circuitry

Postsilicon debug techniques may require e-beam imaging and nanomachining in the vicinity of live metal-oxide semiconductor (MOS) devices. In that context the authors have investigated the invasiveness of e-beam irradiation on MOS devices to 65 nm integrated circuits, tracked as percent change in ring-oscillator frequencies. Device preparation consisted of backside thinning by mechanical polish, local laser chemical etching to 10 mu m Si, and finally, focused ion beam gas-assisted etching, leaving 200-2000 nm remaining Si. This was followed by e-beam exposure at various acceleration energies and doses, from a marginally detectable device degradation dose of 10(-4) nC/mu m(2), and beyond a dose causing total transistor failure around 1.25 nC/mu m(2), at 30 keV. The authors find that relative frequency degradation depends on irradiation dose as a power law which may be applied to limit unwarranted device degradation. E-beam nanomachining is typically performed at low acceleration energies, conveniently reducing the electron penetration depth, and hence a negligible dose makes it to the devices. This was verified experimentally on 65 nm devices. The results herein put upper bounds on damage-free e-beam-based circuit edit and failure analysis in post-Si debug. (C) 2011 American Vacuum Society. [DOI: 10.1116/1.3554904]