Dynamic Vpass Ispp Scheme And Optimized Erase Vth Control For High Program Inhibition In Mlc Nand Flash Memories

Kitae Park,Myounggon Kang,Soonwook Hwang,Youngsun Song,Jaewook Lee,Hansung Joo, Hyunsil Oh,Jaeho Kim,Yeongtaek Lee,Changhyun Kim,Wonseong Lee

2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS（2009）

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摘要

In this paper, dynamic Vpass ISPP schemes and optimizing Vth of erase cells are presented for achieving high program inhibition of sub-40nm MLC NAND flash and beyond. Compared to conventional method, over 40% program failure reduction after 30k P/E cycling was achieved in the proposed scheme. By optimizing erase Vth and its distribution using ISPP-after-erase, about 2 times better Vpass window margin was obtained in 40nm-node MLC NAND test chip.

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helium,stress,degradation,testing,acceleration,electrons,doping,chip

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