Feasibility Study of a 3D IC Integration System-in-Packaging (sip) from a 300mm Multi-Project Wafer (MPW)
J. H. Lau,C.-J. Zhan,P.-J. Tzeng,C.-K. Lee,M.-J. Dai,H.-C. Chien,Y.-L. Chao, W. Li,S.-T. Wu,J.-F. Hung,R.-M. Tain,C.-H. Lin,Y.-C. Hsin,C.-C. Chen,S.-C. Chen,C.-Y. Wu,J.-C. Chen,C.-H. Chien,C.-W. Chiang,H.-H. Chang,W.-L. Tsai,R.-S. Cheng, S.-Y. Huang,Y.-M. Lin,T.-C. Chang, C.-D. Ko,T.-H. Chen,S.-S. Sheu, S.-H. Wu,Y.-H. Chen,W.-C. Lo,T.-K. Ku,M.-J. Kao, D.-C. Hu IMAPSource Proceedings（2011）
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Chip Stacking,System Integration
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