Suppression of the corner effects in a 22 nm hybrid Tri-Gate/planar process

A hybrid Tri-Gate/planar process was investigated by 3-D process and device simulations. Electrostatics of a Tri-Gate and a planar transistor sharing the same well, halo, and S/D have been compared. The suppression of the Tri-Gate corner effect was studied by corner implantation and additional corner rounding after Tri-Gate fin formation. Corner implantation is useful for retargeting Tri-Gate threshold voltage independent of shared planar implantation settings. Corner rounding allows a reduction of electric field overlap, suppressing corner leakage path and improve I ON -I OFF performance.