Channel noise scan for post-layout check of printed circuit board
Asia-Pacific International Symposium on Electromagnetic Compatibility(2015)
Abstract
Channel noise scan (CNS) approach is proposed in this paper to efficiently analyse the potential VR-signal coupling issue in the post-layout printed circuit board (PCB) check and the post-silicon debugging of the platform development. CNS is based on a new simulation methodology that includes the whole PCB with signals, voltage regulator (VR) networks, and the interaction. A frequency domain indicator is proposed to systematically analyse the VR-signal coupling problems. This methodology can also provide the ability for the designer to do performance/cost trade-off, layout optimization.
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Key words
frequency domain analysis,layout,noise,couplings,switches
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