Capacitance-voltage (C-V) characterization in very thin suspended silicon nanowires for NEMS-CMOS integration in 160nm Silicon-on-Insulator (SOI)

We report high-precision, ~femto-Faraday-level (1fF=10 ^-15 F) measurements of capacitance-voltage (C-V) characteristics of suspended and mechanically movable silicon nanowires (SiNWs) with widths down to 50nm, which are coupled to their localized side gate electrodes via nanoscale air gaps. To the best of our knowledge, this effort is the first direct measurement of C-V behavior, combined with analysis and modeling, to extract depletion layer width, within such very thin suspended SiNWs. We observe C-V responses different from those of conventional MOS capacitors and MOSFETs due to the new SiNW structures. We also find that the measured C-V behavior is sensitive to light and frequency of the AC voltage.