Impact of EUV mask surface roughness on LER

Extreme UV lithography or EUVL is still the primary candidate to allow scaling below the 22 nm technological node. Three major engineering challenges need to be simultaneously solved for a smooth introduction of EUVL into high volume manufacturing: source power and reliability, mask readiness, and photoresist performance. For the EUV reticle infrastructure, most of the emphasis to date has been put on obtaining and maintaining a low number of mask defects. However, the reticle flatness requirements for EUV masks are also very stringent. Recent theoretical studies have indicated that multilayer roughness higher than 50 pm causes line edge roughness. In this paper we engineered an EUV mask having a systematic surface roughness aggravation. We exposed this mask on the IMEC ASML NXE:3100, equipped with an USHIO/XTREME discharge-produced plasma (DPP) source. Herein, we present the experimental results illustrating the impact of mask surface roughness on 27 nm half-pitch lines/spaces. No evidence of aggravated line edge roughness was found on the wafer when the mask surface roughness was lower than 500 pm.