A Highly Reliable and Cost Effective 16nm Planar NAND Cell Technology

William Kueber,Giuseppina Puzzilli, Niccolo Righetti, Ricardo Basco, Lin Li,Silvia Beltrami,M Bertuccio,Elisa Camozzi, David A Daycock, Matthew King, Chris Larsen, Jeff Karpan,Akira Goda,Ceredig Roberts

2015 IEEE International Memory Workshop (IMW)（2015）

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Abstract

A 2D 16nm planar NAND cell technology is described with good cell to cell interference and reliability that can be used in a wide variety of applications. This second generation planar cell uses a high-K dielectric stack and a thin poly floating gate to maintain the needed gate coupling ratio and reduce adjacent cell interference. The technology includes select gates with the same planar structure as the cell. This select gate architecture simplifies the manufacturing of this NAND technology.

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Key words

2D planar NAND cell technology,cell to cell interference,reliability,high-K dielectric stack,poly floating gate,size 16 nm

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