Optical DC overlay measurement in the 2nd level process of 65 nm alternating phase shift mask

ABSTRACT Alternating phase shift mask (APSM) techniques help bridge the significant gap between the lithography wavelength and the patterning of minimum features, specifically, the poly line of 35 nm gate length (1x) in Intel’s 65 nm technology. One of key steps in making APSM mask is to pattern to within the design tolerances the 2 nd level resist so that the zero-phase apertures will be protected by the resist and the pi-phase apertures will be wide open for quartz etch. The ability to align the 2 nd level to the 1 st level binary pattern, i.e. the 2 nd level overlay capability is very important, so is the capability of measuring the overlay accurately. Poor overlay could cause so-called the encroachment after quartz etch, producing undesired quartz bumps in the pi-apertures or quartz pits in the zero-apertures. In this paper, a simple, low-cost optical setup for the 2 nd level DC (develop check) overlay measur ements in the high volume manufacturing (HVM) of APSM masks is presented. By removing systematic errors in overlay associated with TIS and MIS (tool-induced shift and Mask-process induced shift), it is shown th at this setup is capable of supporting the measurement of DC overlay with a tolerance as small as +/- 25 nm. The outstanding issues, such as DC overlay error component analysis, DC – FC (final check) overlay correlation and th e overlay linearity (periphery vs. indie), are discussed. Keywords: Mask, APSM, Optical, Overlay, 2