High Performance Transistors Featured in an Aggressively Scaled 45nm Bulk CMOS Technology

Zhengqian Luo,Nivo Rovedo,Soohwan Ong,B Phoong, M J Eller,Henry K Utomo, C Ryou, Huifang Wang,R Stierstorfer,L A Clevenger,Sungho Kim, James J Toomey, D Sciacca,Jie Li,W Wille, Lu Zhao, L Teo,T Dyer, Shaoyun Fang, J D Yan,Ohkyong Kwon,Daelim Park, Jim Holt, Jinguang Han,V Chan, T K J Yuan, Hongseok Lee,Sangrim Lee, A Vayshenker,Zengli Yang,Cuihua Tian,Hioktiaq Ng,H Shang, Matthias Hierlemann,J Ku,J Sudijono,Meikei Ieong

2007 IEEE Symposium on VLSI Technology（2007）

引用 30|浏览7

暂无评分

摘要

An aggressively scaled high performance 45nm bulk CMOS technology targeting graphic, gaming, wireless and digital home applications is presented. Through innovative utilization and integration of advanced stressors, thermal processes and other technology elements, at aggressively scaled 45nm design ground rules, core NFET and PFET realized world leading drive currents of 1150 and 785 uA/um at 100 nA/um off current at 1V, respectively. In addition to the high performance transistors, an ultra low-k back-end dielectric (k=2.4) significantly lowers wiring delay. In this technology, CMOS transistors with multiple-oxide thicknesses are supported for low leakage and I/O operations, and competitive SRAM is offered.

查看译文

关键词

high performance transistors,aggressively scaled bulk CMOS technology,advanced stressors integration,thermal processes,NFET,PFET,low-k back-end dielectric,SRAM,size 45 nm

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要