Design of a Multi-Core SoC with Configurable Heterogeneous 9 CPUs and 2 Matrix Processors

Masami Nakajima,Hiroyuki Kondo,Naoto Okumura,N Masui,Yukari Takata,Takashi Nasu,Hirokazu Takata,T Higuchi,Mamoru Sakugawa, Hirokazu Yoneda,Hayato Fujiwara,Kazuya Ishida,Koichi Ishimi,Satoshi Kaneko, T Itoh,Masayuki Sato,Osamu Yamamoto,Kazutami Arimoto

2007 IEEE Symposium on VLSI Circuits（2007）

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摘要

A multi-core SoC for multi-application (recognition, inference, measurement, control, and security) is developed. The configurable heterogeneous architecture with 9 CPUs and 2 matrix processors reduced 45% power consumption. The performance-oriented multi-bank matrix processor with 2-read-1-write calculation and background I/O operation is adopted. The 1 GHz CPU is realized by the delay management network applied for any kinds of applications and process technologies.

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关键词

multicore SoC design,configurable heterogeneous architecture,CPU,performance-oriented multibank matrix processor,2-read-1-write calculation,background I/O operation,delay management network,frequency 1 GHz

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