Novel 3-Dimensional Integration Technique Of Chip-On-Wafer (Cow) For Mems Applications

The structure of chip-on-wafer (COW) employed off-chip interconnects was successfully fabricated and electrically connected between chips and a base wafer with bump-less contact. The chips were thinned down to 5 mu m and stacked on the base wafer with an adhesive layer. The space between the chips was filled by non-conductive polymer. The through via holes were formed on polymer by Reactive Ion Etching (RIE) and filled up with Copper using Electro-Chemical Deposition (ECD). Lower leakage current as low as back ground was found between the metal pads. No failure and an approximate 100% yield were achieved in the vertical wiring for multi-chips COW stacking.