Numerical Evaluation Of Warpage In Pop Encapsulated Semiconductors

The Package on Package (PoP) emerges as a package alternative to increase the number of transistors in the same area by stacking thin chips. The differences in thermal and mechanical properties of the various materials that constitute the encapsulated chip can result in the device warpage. In this study the thermomechanical behavior of an electronic device encapsulated by the Package on Package technology was simulated. The factors that contribute to generate warping in semiconductor encapsulated with PoP technology during the solder reflow process were evaluated. This study evaluates the conditions and process parameters during fabrication of a 40 gm thick chip molded with one kind of Epoxy Molding Compound (EMC). Through the warpage measurements by Moire interferometry it was possible to build correlations with computer simulation of the device. The results of this comparison were used as a basis for simulation and validation of input data used in other settings for three different thicknesses of silicon chips (40, 100 and 200 microns) and two different types of EMC (EMC1 and EMC2). In the simulations, it was found the warpage of the 40 microns thick chips, considering the different epoxy compounds, decreased by about 40% in the top chip, the reduction obtained in the 100 microns thick chips was in the order of 35%, while in the 200 microns thick chips the warpage decreased by about 3%. The results show the importance of simulation to predict the tendency of warping when there are variations in the fabrication process parameters.