ABR ARCHITECTURE AND SIMULATION FOR AN INPUT-BUFFERED AND PER-VC

This paper proposes an innovative concept, called virtual output queue, to support available bit rate (ABR) traffic on an input-buffered, per virtual circuit (VC) queued switch. This technique allows ABR models developed for output-buffered systems to be migrated to an input- buffered system. In order to evaluate the virtual output queue and to compare different ABR algorithms, a simulator of the ATM testbed at the University of Illinois has been enhanced with ABR functions. This paper provides simulation results for the input-buffered variation of the ERICA+ algorithm.