Cstbt (Tm)(Iii) Having Wide Soa Under High Temperature Condition

Yusuke Fukada,Kenji Suzuki,Tetsuo Takahashi,Tatsuo Harada,Hidenori Fujii,Shinichi Ishizawa,Junichi Yamashita,John F. Donlon,Tomohide Terashima

2011 IEEE 23RD INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD)（2011）

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摘要

This paper presents high temperature performance of CSTBT (TM) (III) and its main parameters. The key for high temperature operation is suppressing the parasitic NPN transistor action. N+ emitter width, P+ diffusion layer depth and gate oxide thickness are main parameters for suppressing the parasitic action. The optimized 1200V CSTBT (TM)(III) succeeded in 200 degrees C operation without any thermal runaway or turn-off failure.

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关键词

insulated gate bipolar transistors,power bipolar transistors,carrier stored trench gate bipolar transistor,diffusion layer depth,emitter width,gate oxide thickness,high-temperature operation,parasitic NPN transistor action,temperature 200 degC,thermal runaway,turn-off failure,voltage 1200 V,

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