On-Chip Transformer Using Multipath Technique With Arithmetic-Progression Step Sub-Path Width

A novel on-chip transformer architecture using multipath technique is presented. The newly proposed arithmetic-progression step sub-path width method is used to lower the current-crowding effect induced by the difference between the length of inner sub-path and that of outer sub-path. Full-wave electromagnetic simulated and measured results confirm the better performance of the proposed transformers than the conventional ones. These transformers will be useful in designing high-performance CMOS RF integrated circuits for wireless applications.