Low temperature dielectric deposition for via-reveal passivation

This paper reports on the development of low temperature (<190 degrees C) plasma-enhanced chemical vapour deposition (PECVD) processes used to deposit silicon oxide / silicon nitride film stacks for use as passivation layers over exposed through-silicon vias in thinned (<60 mu m), 300mm silicon wafers, temporarily bonded to silicon or glass carriers. The deposition processes are optimized to provide excellent electrical isolation with the films having low leakage currents and high breakdown voltages. The deposited stacks are also used to compensate for wafer bow resulting from CMOS front-side wafer processes and so provide a method of preventing excessive bow when the thinned silicon wafer is de-bonded from its carrier. Crucially, electrical properties and stack stress are shown to be stable with no drift over time when exposed to atmosphere.