PMOSFET layout dependency with embedded SiGe Source/Drain at POLY and STI edge in 32/28nm CMOS technology

Liyang Song,Yue Liang, H. Onoda, C. W. Lai,Thomas A. Wallner,A. Pofelski, Christian Gruensfelder,Emmanuel Josse, T. Okawa, J. Brown, R.Q. Williams,Judson R. Holt, J.W. Weijtmans,Brian J. Greene,Henry K. Utomo, Shin-Ae Lee,Deleep R. Nair,Qintao Zhang,Chendong Zhu,X. Wu, Melanie J. Sherony,Y. M. Lee,William K. Henson,R. Divakaruni,E. Kaste

international symposium on vlsi technology, systems, and applications（2012）

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摘要

The eSiGe layout effect induced by PC-bounded or STI-bounded eSiGe shows impact on device performance and variability increase. For PC-bounded device, performance degradation could be explained by the mobility loss due to reducing eSiGe volume and less stress strength. For STI-bounded device, performance degradation varies, due to strong interaction between eSiGe fill morphology and device overlap capacitance. This observation was confirmed by an eSiGe fill level study. Compared to PC-bounded eSiGe, STI-bounded devices have increase variation due to eSiGe process.

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关键词

stress,cmos technology,logic gate,logic gates,very large scale integration,cmos integrated circuits,degradation,layout,morphology

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