Timing Variability Analysis For Layout-Dependent-Effects In 28 Nm Custom And Standard Cell-Based Designs

We identify most recent sources of transistor layout dependent effects (LDE) such as stress, lithography, and well proximity effects (WPE), and outline modeling and analysis methods for 28 nm. These methods apply to custom layout, standard cell designs, and context-aware post-route analysis. We show how IC design teams can use a model-based approach to quantify and analyze variability induced by LDE. We reduce the need for guard-bands that negate the performance advantages that stress brings to advanced process technologies.