Ultra high-speed 0.25-/spl mu/m emitter InP-InGaAs SHBTs with f/sub max/ of 687 GHz
international electron devices meeting(2004)
摘要
We have developed novel but simple process techniques for high speed InP SHBTs. For parasitic reduction, the collector layer is undercut using an etch-stop layer, the base pad is isolated, and the emitter metal is widened using thick plated gold. For transit time reduction, the SHBT employs InGaAs base with graded In-composition and InGaAlAs emitter setback with graded Al-composition. Maximum extrapolated f/sub max/ of about 687 GHz with f/sub T/ of 215 GHz is achieved for 0.25 /spl times/ 8 /spl mu/m/sup 2/ emitter area devices at I/sub c/ = 8 mA and V/sub ce/ = 15 V. This data clearly shows that the optimized conventional process can offer direct implementation of InP HBT for high-speed electronic circuit fabrication.
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关键词
integrated circuit layout
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