Double Patterning Optimization In 20nm Sram Design

As the semiconductor critical dimension (CD) is shrunk to 20nm node and beyond, double and triple patterning technologies become necessary for current 193nm optical lithography. However, the new technologies induce a new variation factor of the two or three mask pattern mismatching in terms of the wafer CD or alignment performance on silicon. This mismatch can degrade matching circuit performance such as SRAM and analog circuit. In this paper, we address the impact on our 20nm CRAM (configuration RAM used in FPGA circuit) performance caused by diffusion layer pattern decomposition (coloring). Furthermore, we propose a methodology to optimize the coloring based on an alignment performance assessment and CD control of two mask patterns printed on silicon wafer. In the same experiment, we observed that the OPC (Optical Proximity Correction) is also critical to the coloring methodology. The silicon results show that after the optimization, the impact of coloring-induced mismatch on CRAM performance can be reduced significantly.