Enhancing Component Level Reliability Of Pb-Free Flip Chip Package Of Cu/Low-K Devices Using Fem-Based Sensitivity Analysis

As the Cu/low-k interconnects integrated into the next-generation IC chip, particularly for devices below 90nm, to meet the requirements of reducing RC time delay and low power consumption, how to establish a feasible and robust solution of packaging technology regarding to the structural design as well as the material selection of packaging components has become more important to fulfill the fast progress of semiconductor industry. Although eutectic Sn-Pb solder is the mainstream interconnections between components at present, due to environmental issues with the Pb ingredient of the Sn-Pb solder, the electronic industry tends to utilize Pb-free solder. At this time, the nature of low-k materials and the replacement of Pb-free solder greatly increase the complication in ensuring the enhancement of packaging level reliability. The foregoing urgent issue needs to be quickly resolved when developing various advanced packages. To this end, the prediction model of fatigue life for Pb-free solder joint combined the virtual design of experiment (DOE) with factorial analysis is used to obtain the sensitivity information of selecting geometry/material parameter in the proposed low-k flip-chip (FC) package. Moreover, a three-dimensional (3D) nonlinear strip finite element (FE) model combined with the two levels of specified boundary condition (SBC) of global-local technique is adopted to shorten the time of numerical calculation as well as to possess an accurate solution. The results of the thermal cycling in the experimental test show good agreement with the simulated analysis. Moreover, the sensitivity of analysis indicates the type of underfill material has a significant effect on the Pb-free solder joint reliability. Furthermore, a suitable combination of concerned designed factors is suggested in this research to enhance the reliability of Cu/low-k FC packaging with Pb-free solder joints.