Effect of top gate bias on NBIS in dual gate a-IGZO TFTs
2015 22nd International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD)（2015）
Abstract
We report the effects of top gate bias (V
TG
) on negative bias illumination stress (NBIS) applied at bottom gate terminal in dual gate amorphous indium gallium zinc oxide (a-IGZO) thin film transistor (TFT), while transfer characteristics measured at bottom gate terminal before and after stress. NBIS in a-IGZO TFTs show negative transfer shift due to the formation of positive charges, likely ionization of oxygen vacancies (V
O
→ V
O
+
/V
O
2+
) and/or hole traps in Gate insulator/a-IGZO interface and a-IGZO bulk. We observed -3.26V shift after NBIS, for -10V bias at VTG, which decreases to -1.3V for V
TG
= +10V. It clearly revels the formation of less defects in IGZO channel when the Fermi level is shifted upward by positive top gate bias.
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Key words
top gate bias,NBIS,dual gate a-IGZO TFT,negative bias illumination stress,bottom gate terminal,thin film transistor,transfer characteristics,negative transfer shift,oxygen vacancies,Fermi level,voltage -3.26 V
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