Formation Of Sub-10 Nm Width Ingaas Finfets Of 200 Nm Height By Atomic Layer Epitaxy

D. Cohen-Elias, J. J. M. Law, H. W. Chiang,A. Sivananthan, C. Zhang,B. J. Thibeault,W. J. Mitchell,S. Lee,A. D. Carter, C. -Y. Huang,V. Chobpattana, S. Stemmer,S. Keller,J. W. Rodwell

2013 71ST ANNUAL DEVICE RESEARCH CONFERENCE (DRC)(2013)

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摘要
As FETs are scaled, the dielectric and semiconductor channel thicknesses must be reduced to suppress short-channel effects. Even using fin field effect transistors (finFETs) and gate all around FETs (GAAFETs), [1],[2], whose electrostatic performance is excellent, at 4nm gate length the channel should be less than 2nm thick. To obtain high drive current per unit IC die area, the fin height should be many times the fin pitch, i.e. tens to hundreds of nm. Dry-etching a fin of few-nm width and > 100 nm height presents severe challenges in control of etch sidewall slope and in minimizing surface damage. Here we report an InGaAs finFET fabrication flow which form fins of sub-10nm width and 200 nm height. Fin width is controlled by atomic layer epitaxial (ALE) growth and by semiconductor selective crystallographic wet etching. We further demonstrate self-aligned source-drain regrowth in this process [3],[4]. This facilitates scaling of the source/drain pitch to small dimensions.
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关键词
atomic layer epitaxy,etching,tin,logic gates,gallium arsenide
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