Scaling Of 32nm Low Power Sram With High-K Metal Gate

This paper describes SRAM scaling for 32nm low power bulk technology, enabled by high-K metal gate process, down to 0.149 mu m(2) and 0.124 mu m(2). SRAM access stability and write margin are significantly improved through a 50% Vt mismatch reduction, thanks to HK-MG T-inv scaling. Cell read current is increased by 70% over Poly-SiON process. Ultra dense cell process window is expanded with optimized contact process. A dual-ground write assist option can additionally enable ultra dense 0.124 mu m(2) cell to meet low power application requirements.