Short-Flow Test Chip Utilizing Fast Testing For Defect Density Monitoring In 45nm

Muthu Karthikeyan, William Cote,Louis Medina,Ernesto Shiling, Arthur Gasasira, Amy Henning,William Ferrante,Mark Craig, Thomas Merbeth

2008 IEEE INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES, CONFERENCE PROCEEDINGS(2008)

Cited 7|Views26
No score
Abstract
A comprehensive 45nm short-flow test chip was designed and is currently used to improve defect-limited yield. In a novel development to reduce test time, the DC test structures are tested in parallel mode on a functional test platform, resulting in a 5x reduction in test time over conventional parametric testing. The large critical area enables accurate measurement of defect densities down to the ppb-level, while the reduced cycle time of this short-flow test chip makes it an excellent routine defect monitor as well as a test vehicle for evaluating process changes.
More
Translated text
Key words
yield enhancement,defect-limited yield,process characterization,parallel-test
AI Read Science
Must-Reading Tree
Example
Generate MRT to find the research sequence of this paper
Chat Paper
Summary is being generated by the instructions you defined