Material choice for optimum stress memorization in SOI CMOS processes

Stress engineering has become the sine qua non of any advanced CMOS technology since the 90nm technology node. In this paper, we focus on the influence of material properties and anneal sequences on the benefit of the stress-memorization technique for SOI CMOS transistors. We distinguish between low- and high-temperature stress memorization. Film hardness, stress level, and the order of anneals are found to play an important and partially very different role for these two improvement mechanisms.