A 150 MHz bandwidth continuous-time ΔΣ modulator in 28 nm CMOS with DAC calibration

This paper presents transistor-level design of a 150 MHz bandwidth continuous-time (CT) ΔΣ modulator in a 0.85 V 28 nm CMOS process. Architectural-level design tradeoff for the high bandwidth requirement is discussed. A stand-alone DAC calibration scheme that suits the high-speed modulator is proposed for linearization. Simulation results show that the modulator achieves signal-to-noise-and-distortion ratio (SNDR) of 71 dB and spur-free dynamic range (SFDR) of 90 dB.