A Novel Two-Transistor Floating-Body Memory Cell
2007 IEEE International SOI Conference(2007)
摘要
In this paper we propose a novel two-transistor (2T) FBC for DRAM applications that can yield much better signal margin and density, while offering other significant advantages over the 1T cell. The key features of the 2T FBC are demonstrated via process/physics-based device/circuit simulations, supported by numerical results.
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关键词
SOI MOSFET,circuit simulations,signal density,signal margin,DRAM applications,2T FBC,two-transistor floating-body memory cell
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