COBRA: an 1.2 million transistor expandable column FFT chip

Glen Sunada,Jain Jin,Matt Berzins,Chen, T.

Cambridge, MA（1994）

引用 30|浏览8

暂无评分

摘要

This paper presents an optimized column FFT architecture which utilizes bit-serial arithmetic and dynamic reconfiguration to achieve a complete overlap between computation and communication. As a result, the system can compute a 24-bit precision 1 K point complex FFT transform within 9.25 μs, far surpassing the performance of any existing FFT systems

查看译文

关键词

digital arithmetic,digital signal processing chips,fast Fourier transforms,signal processing,1.2 million transistor expandable column FFT chip,24-bit precision,COBRA chip,bit-serial arithmetic,dynamic reconfiguration,optimized column FFT architecture

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要