Parallel-Sampling Adc Architecture For Multi-Carrier Signals

This chapter starts with a brief introduction of broadband multi-carrier transmission in Sect. 3.1. Section 3.2 describes the amplitude properties of multi-carrier signals, especially their large peak-to-average ratio. A discussion of the ADC dynamic range requirement for a multi-carrier system is given in Sect. 3.3. Section 3.4 reviews power reduction techniques to enhance the SNR of noise limited ADCs in advanced CMOS technologies. Section 3.5 presents a parallel-sampling architecture for ADCs to convert multi-carrier signals efficiently by exploiting their amplitude statistical properties. ADCs with this architecture are able to have a larger input signal range without causing excessive distortion while showing an improved accuracy over the small amplitudes that have much higher probability of occurrence due to the multi-carrier signal amplitude properties. The power consumption and area of ADCs with the parallel-sampling architecture can be reduced to achieve a desired SNR for multi-carrier signals compared to conventional ADCs. Section 3.6 proposes four implementation options of the parallel-sampling ADC architecture and Sect. 3.7 concludes the chapter.