Design of a Fast Locking Delay-Locked-Loop with Timing Skew Self Calibration Based on 65 nm CMOS Process

This paper proposes a fast locking Delay-Locked-Loop (DLL) with background timing skew calibration. By using the reverse conducting property of MOSFET in charge pump, the proposed architecture reduces the locking time while the complexity of the circuit remains unchanged. In addition, a self-calibration algorithm for timing skew based on charge pump is designed. It detects the timing skew by capacitor through charge pump and compensates the timing errors adaptively in background. The proposed DLL is designed in a 65 nm CMOS process. The post-layout simulation shows that the locking time is reduced from 592 ns to 77 ns. The maximum timing skew is minimized from 34 ps to 2 ps. The rms jitter and peak-to-peak jitter are 0.63 ps and 3.18 ps, respectively.