(Invited) Aspect Ratio Trapping: A Unique Technology for Integrating Ge and III-Vs with Silicon CMOS

This paper describes the recent development of the Aspect Ratio Trapping (ART) heterointegration technique. This technique uses high aspect ratio sub-micron trenches to trap threading dislocations, greatly reducing the dislocation density of lattice mismatched materials grown on silicon. ART is shown to be very effective for a wide variety of materials including Ge, GaAs and InP. It has been combined with epitaxial lateral overgrowth to create long, 18 mu m wide strips of low dislocation density material. ART has been used to integrate many types of Ge and III-V devices on silicon including GaAs MOSFETs, GaAs lasers, GaAs tunnel diodes and a silicon infrared imager chip with monolithically integrated Ge photodiodes.