High Speed Interface For Digital Centric Transmitters

This paper presents a high-speed serial PLL-less interface suitable for usage in mobile transmitters. The interface uses current mode signaling to reduce both ground bouncing and the crosstalk impact on the mobile frontend. A digital controlled delay line is employed to adjust the sampling point of the highspeed serial clock. The data is 8b/10b encoded for word recovery and signaling of configuration packets. The interface is self-initializing and distinguishes between signal and configuration data. It consists of three lanes from the FPGA to the ASIC and one lane in backward direction to debug the internal ASIC signals. The interface is able to transfer up to 1.6 Gbit/s per lane. It consumes 3 mA from a 1.2 V supply.