Germanium n-Channel Planar FET and FinFET: Gate-Stack and Contact Optimization

Mark J H Van Dal,B Duriez,G Vellianitis,G Doornbos,Matthias Passlack,Yeechia Yeo,Carlos H Diaz

IEEE Transactions on Electron Devices（2015）

引用 20|浏览52

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摘要

We demonstrate Ge enhancement-mode nMOS FinFETs fabricated on 300-mm Si wafers, incorporating an optimized gate-stack (interface trap density Dit below 2 × 1011 eV-1 · cm-2), n+-doping (active doping concentration Nact exceeding 1 × 1020 cm-3), and metallization (contact resistivity Pc below 2 × 10-7 Ω · cm2) modules. A new circular transmission line Pc extraction model that captures the parasitic...

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关键词

Logic gates,Resistance,FinFETs,Junctions,Annealing,Nickel

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