Eliminate the X-Optimization during RTL Verification

Verification of complex SoC designs suffers from X-optimization issues that often conceal design bugs. The deployment of low power techniques such as power-shutdown in today's SoC designs exacerbate these X-optimism issues. To address these problems we adopted a new simulation semantic that more accurately models non-deterministic values in logic simulation. In this paper we discuss how to eliminate the X-optimism during RTL verification.