A 3.8 mW/Gbps quad-channel 8.5–13 Gbps serial link with a 5-tap DFE and a 4-tap transmit FFE in 28 nm CMOS

Ali, T.,Rao, L.,Singh, U.,Abdul-Latif, M.

VLSI Circuits（2015）

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摘要

This paper presents a quad-lane serial link that supports virtually all data center system-side and line-side communications standards from 8.5-13 Gbps, implemented in 28 nm CMOS. The Tx is series source terminated with a 4-tap FFE. Its swing ranges from 33 mV to 1 Vppd. The Rx has CTLE, 5-tap DFE and CDR with 2x-oversampling, and baud-rate timing recovery options. At 13 Gbps, the link can equalize 35 dB loss at Nyquist frequency with BER of 10-12. The link consumes 49 mW per lane at 13 Gbps. This is the lowest reported power in its class to date, and with comprehensive programmability for a wide range of standards.

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关键词

CMOS integrated circuits,data communication equipment,decision feedback equalisers,mixed analogue-digital integrated circuits,CMOS integrated circuit,DFE,baud rate timing recovery,bit rate 8.5 Gbit/s to 13 Gbit/s,continuous time linear equalizer,data center line side communication,data center system side communication,decision feedback equalizer,feed forward equalizer,power 3.8 mW,power 49 mW,quad channel serial link,quad lane serial link,size 28 nm,transmit FFE

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