Development of pipelined polynomial multiplier modulo irreducible polynomials for cryptosystems

In this paper, we consider a schematic solution of the pipeline multiplier modulo, where multiplication begins with the analysis of the lowest order of the polynomial multiplier, which can serve as an operating unit for high-speed encryption and decryption of data by hardware implementation of cryptosystems based on a non-positional polynomial notation. The functional diagram of the pipeline and the structure of its logical blocks, as well as an example of performing the operation of multiplying polynomials modulo, are given. The correct functioning of the developed circuit was checked by modeling in the Vivado Design Suite computer-aided design for the implementation of the multiplication device on the development/evaluation kit Artix-7 based on the Spartan 6 field-programmable gate array series by Xilinx. The effectiveness of the proposed hardware pipeline multiplier in modulo is confirmed by the Verilog Testbench timing diagram implemented for the evaluation kit Artix-7 field-programmable gate array. In addition, the developed pipelined modulo multiplier takes no more than 0.02 % of the resources of the used field-programmable gate array for a given length of input data. Compared to the matrix multiplication method, a pipelined modulo multiplier can handle a large data stream without waiting for the result of the previous multiplication step. The modulo pipelined multiplier depth depends on the bit width of the input data. The developed pipeline device can be used in digital computing devices operating in a polynomial system of residue classes, as well as for high-speed data encryption in blocks of cipher processors operating on the basis of a non-positional polynomial number system.