Structural design, layout analysis and routing strategy for constructing IC standard cells using emerging 3D vertical MOSFETs

As optical lithography and conventional transistor structure are approaching their physical limits, 3D vertical gate-all-around (GAA) nanowire MOSFETs and double-surrounding-gate (DSG) MOSFETs are two promising device candidates for post-FinFET logic scaling owing to their superior gate control and scaling potential. However, source, drain and gate of a vertical nanowire MOSFET and DSG MOSFETs are located in different physical layers. Consequently, structural design of IC devices/circuits, layout arrangement for high-density vertical nanowires/interconnects, and routing strategy are non-trivial challenges. In this paper, we shall discuss these critical issues for constructing standard cells using 3D vertical GAA nanowire MOSFETs and DSG MOSFETs. We redesigned the standard cells in Nangate Open Cell Library for 5nm node using vertical GAA nanowire MOSFETs and DSG MOSFETs. Experimental results verify the functionality of the proposed standard cell layout design approach. © 2016 SPIE.