A 27% Active And 85% Standby Power Reduction In Dual-Power-Supply Sram Using Bl Power Calculator And Digitally Controllable Retention Circuit

Keiichi Kushida,Fumihiko Tachibana,Osamu Hirabayashi,Yasuhisa Takeyama,Miyako Shizuno,Atsushi Kawasumi,Azuma Suzuk,Yusuke Niki,Shinichi Sasaki,Tomoaki Yabe,Yasuo Unekawa

PROCEEDINGS OF THE 2013 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)（2013）

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摘要

This paper presents SRAM circuit techniques to reduce both active and standby mode power especially at room temperature (RT) where actual power consumption is dominant. A bit line power calculator is used to adaptively set the cell supply voltage (Vcs) in the active mode. A digitally controllable retention circuit regulates Vcs in the standby mode with small control power. These circuits are implemented in a dual-power-supply SRAM in 28 mn CMOS technology. Compared with the conventional scheme, the power consumption in the active and standby mode at 25 C is reduced by 27% and 85%, respectively.

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关键词

CMOS memory circuits,SRAM chips,low-power electronics,power consumption,BL power calculator,CMOS technology,RT,SRAM circuit techniques,active mode power reduction,bit line power calculator,cell supply voltage,control power,digitally controllable retention circuit,dual-power-supply SRAM,power consumption,room temperature,size 28 nm,standby mode power reduction,temperature 25 C,temperature 293 K to 298 K,

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